1. Field of the Invention
The invention relates to a power MOSFET having a plurality of cells connected in parallel disposed on a semiconductor body; each of the cells comprises a gate zone and a source zone embedded in planar fashion in the gate zone; the assembly has a metallization layer that contacts the gate zones through contact holes formed in the source zones, and gate electrodes that are connected in parallel.
2. Description of the Related Art
A power MOSFET of this general kind has been described in European published patent application 0 293 846 A1, for example. In that teaching, the object is to increase the avalanche current, which typically flows at the edge of the cell field, without turning on the parasitic bipolar transistor and thereby destroying the transistor. It was proposed in the European document to produce a source zone which would help avoid damage due to overload, and more specifically to provide the cells of the cell field adjacent the edge without a source zone or with a source zone of decreased size.
Since power MOSFETs in general are manufactured by a self-aligning technique, in that the gate electrodes form the implantation mask for both the gate and the source zones, that prior art semiconductor component requires one additional mask.